1. Field of the Invention
The present invention relates to data storage subsystems which are attachable to host processors, particularly those data storage subsystems employing a cache (fast access data storage portion) interposed between the host processors and a backing store. Typically a backing store is a disk recorder, such as a magnetic or optical disk unit.
2. Discussion of the Prior Art
Peripheral data storage hierarchies have been used for years for providing an apparent store as suggested by Eden et al in U.S. Pat. No. 3,569,938. Eden et al teach that in a demand paging or request system, caching data in a high-speed front store (also termed a buffer) can make a peripheral data storage subsystem appear to have a large data storing capacity yet provide for more rapid access to data than would be provided by a usual backing store, such as a disk recorder. Eden et al also teach that the backing store can be retentive, such as magnetic tape recorders and disk recorders, while a front store can be a volatile store, such as a magnetic core store. With advances in data storage technology, the front store now typically includes a semiconductive-type data storage elements, for example as seen in U.S. Pat. No. 3,839,704.
A main purpose in providing the cache is to enhance the performance. Enhanced performance means reduced access time to any requested unit of data, as well as providing faster transfer of the data from the data storage subsystem to a requesting host processor, or in the reverse, accepting data at a faster rate than would be provided if the host processor were directly recording into a backing store. One of the problems in providing such enhanced performance is that computer programs or processes executed in the host processor have different operational characteristics. That is, some programs will access and record data in what can be termed a random access mode. In such instances, the amount of data sequentially transferred is minimal. A set of references or accesses to the data typically do not involve large amounts of data but "randomly" access data storage locations. Other computer processes executed in a host processor sequentially access large amounts of data which are processed quickly such that the input/output rate of the host processor is extremely high. If the cache and the residency of data in the cache are designed to enhance the operation of the random access processes, then the performance of the highly sequential processes are degraded. Of course it should also be realized that computer processes demand different I/O characteristics intermediate the random and sequential processing. All of these differences result in differing host processor performances using a cached peripheral data storage subsystem.
Attempts have been made to improve the performance for both random and sequential processes by having the host processor indicate to the data storage system whether the process results in a random I/O procedure or a sequential I/O procedure. One such arrangement is shown by Bastian et al in U.S. Pat. No. 4,466,059. Reference is made particularly to FIG. 3 of Bastian et al. There, Bastian et al teach that the data processing input/output operations are handled in so-called chains of command. Such chains of command are generated by a so-called channel processor within the host processor. Upon the completion of one chain of peripheral operations, corresponding to the execution of a single channel program, a control unit managing the cache and the backing store (in the case of Bastian et al they illustrate a magnetic disk recorder as the backing store) the character of the data transmissions in the just previously executed chain of peripheral operations is examined. Included in this examination is whether or not the host processor supplied a sequential bit, i.e., indicate that the I/O process is to be an input/output sequential operation. Also, the types of data recording operations were examined, i.e. were there combinations of recording operations with the sequential bit. Then certain tracks of data (a track of data is the amount of data storable on one track of the magnetic disk recorder) are deleted from the cache, i.e., transferred from the cache to the backing store and erased from the cache. Also, it was examined whether or not any writing by a host processor occurred during the chain of operation, i.e., did the host processor only read data from the subsystem? If reading only occurred and a sequential bit is set, then the next track of the disk recorder is transferred to cache. It should be remembered that in sequential data, the normal process for a host processor to process the data is to go from a low address to a higher address in any data storage unit. Accordingly, a next track means a track having a backing store address one greater than the backing store address of the track currently being accessed in the cache. Of course, if such next track is already resident in the cache, it would not be promoted from the backing store to the cache store. In the arrangement taught by Bastian et al, the just-described operations are performed immediately upon the conclusion of the chain peripheral operation or immediately before a chain of operation is to be next executed. The advantage of the latter is that it could avoid unnecessarily promoting one track of data to the cache. The Bastian et al patent appears to be directed toward primarily random type of computer processes, i.e., the teaching is that write hits are to be discouraged and read hits are to be encouraged. The addition of the sequential bit is an accommodation and a recognition that sequential data processing is important, and it is important to have reasonable performance for such sequential data processing.
While the Bastian et al technique provides for enhanced performance for many computer processes, there are still many computer processes that could be enhanced further by improving the sequential processing of data in the data storage subsystem such that the computer process would not have to wait for completion of data transfers. It is also desired that a sequential mode of operation be implicitly detected rather than always require the host processor to command or declare a sequential mode of operation for each and every computer process that would benefit from a sequential mode of operation.
An example of a data promotion scheme adapted primarily for a high rate of sequential processing is shown in Tayler, U.S. Pat. No. 4,414,644. Tayler requires that the host processor not only indicate that data is to be sequentially processed but also the extent of that data to be sequentially processed. That is, an entire locality of references for a given computer process is declared to the data storage subsystem. In this event, when the host accessed to the cache results in a cache miss on a read operation, then all of the data to be found in an immediate locality of references that was declared to the data storage subsystem are promoted to cache. While this procedure certainly enhances a high rate of sequential processing, it also uses an extremely large amount of cache data storage space. Since a large number of computer processes may be sharing the cache, such large usage for a single process may be detrimental to the efficiency of a data processing installation. Therefore, the use of Tayler technique for sequential processing is useful in certain situations, but is not necessarily efficient in other data processing situations.
It is also to be recognized that magnetic disk recorders have been used for years with host processors. Accordingly, many computer processes which were established long before caching was commonly used in a peripheral data storage subsystem optimized the computer process by accommodating the physical parameters of magnetic disk recorders. Such physical parameters include latency time of the disk rotation and the seek time in changing from one set of tracks to another plus the knowledge of data storing cylinders, i.e., a set of tracks having a common radius on a set of stacked record disks mounted on a common spindle for rotation. Such cylinders resulted in almost zero track switch time in that electronic circuits were used to switch between the various transducers on the respective data storing surfaces of the disk within a single cylinder of tracks. Based upon this knowledge, certain computer processes transfer data from a complete cylinder of tracks as a single multitrack I/O operation. In such a multitrack operation, the intervention of a cache store in the data transfer process normally increases the access time, thereby unintentionally reducing performance of computer process. It is desired to avoid such degradation of performance for any program.
Accordingly, a plurality of modes of operation which are implicitly determined are desired for a cached peripheral data storage subsystem.
Tobias in U.S. Pat. No. 3,898,624 shows a processor cache interposed between host processor circuits and a so-called main memory. The cache occupancy is determined by an operator using a system console of the system The system console indicates to the cache control circuits of the processor cache the type of prefetching required for enhancing the performance of a given computer process currently being executed. Tobias provides for eight different states based upon the operations to be performed. The eight states have different prefetch characteristics for enhancing the respective computer processes. For example, instruction prefetch has different prefetch characteristics than an operand prefetch, which is different in turn from a "channel" prefetch. Such operations are commanded from the system console, i.e., are effectively manually selected. While such differing prefetches are tuned to the type of operation do provide enhanced performance, it is desired to accommodate other parameters which affect differing input/output data rates in sequential data processing. For example, a peripheral data storage subsystem can be attached to a plurality of host processors. Each of the host processors can have a different computing capability resulting in differing data rates in their respective input/output (I/O) operations. For example, if the same program or process were executed in a highly capable host processor, a relatively high input/output rate would be demanded to provide for efficient process execution. This I/O operation requires a greater amount of prefetch independent of the type of program or operation being performed. In contrast, when such a program is executed on a lower capacity host processor, then the input/output sequential rate could be reduced. It is desire, therefore, to implicitly determine the rate of sequential processing in a host processor and adjust peripheral data storage operations in accordance with such implicit determination of host processor execution rates.